1. Field of the Invention
The invention relates to semiconductor memories and in particular to channel erase and program for a semiconductor nonvolatile device such as a one-transistor, NOR-type semiconductor integrated circuit device comprising a flash electrically erasable programmable read only memory (EEPROM).
2. Description of the Related Art
In today""s leading flash EEPROM technology, a plurality of one-transistor EEPROM cells has been configured into either NAND-type or NOR-type arrays. For NAND-type cell array, the flash cells"" sources and drains are mutually connected in series to save die size for the reason of cost reduction. In contrast, for NOR-type cell array, the cells"" drains and sources are connected in parallel to respective bit lines and source lines to achieve high read speed at sacrifice of die size increase. It is well known that the NAND-type cell array suffers no over-erase problem due to its unique array structure allowing no leakage path during read. For one-transistor (non-split gate) NOR-type cell array, the over-erase problem may or may not occur and is fully subject to the choice of erase and program methods. Conventionally, program is performed on the basis of bit-by-bit method but erase is performed collectively on all cells of the block. In either NOR-type or NAND-type flash memory, the entire flash chip is divided into several blocks. Typically, the size of each flash block ranges from 64 Kbits to 512 Kbits. The erase operation is normally performed prior to program operation. In NAND-type flash memory, the erase is performed by block(sector) basis and program is performed by page basis. A page is usually defined as a word line and a block is defined as many word lines which share common bit lines within the same divided block. Although several methods of erase and program operations have been proposed before, in the current NAND-type flash memory, the definition of erase and program operations is unified. The erase operation is to decrease the Vt of the cells that are physically connected to the same erased word line or the word lines in the same block. In contrast, the program operation is to increase Vt of cells of selected erased word line or word lines in the selected block. The non-selected cells in the non-selected word lines in the selected block or the non-selected blocks remain undisturbed.
The following U.S. patents of prior art are directed toward the detailed description of NAND type flash EPROM""s.
A) U.S. Pat. No. 6,038,170 (Shiba) is directed toward a nonvolatile memory of a hierarchical bit line structure having hierarchical bit lines which includes a plurality of sub-bit lines.
B) U.S. Pat. No. 5,464,998 (Hayakawa et al.) is directed toward a non-volatile semiconductor memory device including NAND type memory cells arranged in a matrix pattern over a semiconductor substrate.
Up to the present, the definitions of erase and program operation for one-transistor NOR-type flash memory remain inconsistent. Erase could be defined to increase the Vt of the cells and program to decrease the Vt of the cells or vise versa depending on preferable flash technology and its design techniques. The following is a summary of erase and program operations for state of the art one-transistor (non-split-gate) NOR-type flash EEPROM technologies.
1) Fowler-Nordheim (F-N) edge-erase, CHE edge-program, One-Transistor, NOR-type flash EEPROM technology. The typical example is an ETOXTM flash cell. In this prior art, the program is performed on bit-by-bit basis to increase cell""s Vt by using CHE (Channel-Hot-Electron) method while erase is performed on block basis to decrease cell""s Vt by using FN-tunneling method. The CHE program consumes more than 300 xcexcA per bit, therefore only a few bits can be programmed at a time by an on-chip charge pump of economic area. Unlike CHE, FN-tunneling erase requires only 10 nA per flash cell so that a big block size of 512 Kb can be erased simultaneously. For 3V or lower Vdd operation, about 4 bits of ETOXTM cells are programmed in state-of-the art design. In the CHE operation, hot electrons are injected into cell""s floating gate with an increase in Vt. In contrast, for a FN-tunneling operation, the electrons are extracted out of the floating gate with a decrease in Vt. The erase operation is called edge-erase operation, which is done at the edge of the thin tunnel-oxide between the floating gate and the source junction. In this ETOXTM flash cell, the source junction of N+ is used for erase operation only and is made to be much deeper than the drain junction. The source junction of N+ is surrounded with lightly-doped N-implant to reduce the peak electrical field as generated during erase operation at the tunneling edge. The drain junction is formed with shallow N+, with P+ implanted underneath to enhance the electrical field for CHE program. The ETOXTM cell is made non-symmetrical with respect to source and drain junctions of the cell in terms of cell structure and operating conditions; therefore it is very difficult to be shrunk below 0.18 xcexcm technology for Ultra-high integrated memory.
The key operating conditions for this technology with a cell made on P-substrate are summarized below:
The drawbacks of this ETOXTM flash cell are: a) low cell scalability caused by an asymmetrical cell structure with deep source junction, b) high program current caused by the CHE program scheme, c) high erase current caused by the edge-FN scheme with large substrate leakage current, d) severe over-erase issue caused by the decrease in the Vt of the cells during erase operation, and e) severe channel punch-through problem in shorter channel length devices caused by edge erase.
The following U.S. patents of prior art are directed toward the detailed description of ETOXTM flash cell operations:
A) U.S. Pat. No. 5,712,815 (Colin et al.) is directed toward An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided.
B) U.S. Pat. No. 5,790,456 (Haddad) is directed toward an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation.
C) U.S. Pat. No. 6,011,715 (Pasotti et al.) is directed toward a programming method for a nonvolatile memory which includes several steps that are repeated until a final threshold value is obtained.
D) U.S. Pat. No. 5,825,689 (Wakita) is directed toward a nonvolatile semiconductor memory device including a memory cell array in which the threshold voltage of a transistor constituting the memory cell is the ground potential or less, and the source voltage condition is changed by a source potential setting circuit in accordance with a detection result from a data detecting circuit.
2) FN channel-erase, FN edge-program, one-transistor, NOR-type flash EEPROM technology. The representative example of this type flash is an ANDTM flash cell. Unlike ETOXTM technology, the program is performed on bit-by-bit basis to decrease cell""s Vt while erase is performed on block basis to increase cell""s Vt. This operation eliminates the over-erase problem of the ETOXTM technology. Both erase and program operations use the FN-tunneling method, which consumes only about 10 nA per bit without taking the much greater substrate current into account. Therefore a large number of flash cells within a big block can be programmed and erased simultaneously by on-chip charge pump of economic area. For single low power supply Vdd of 3V or below, as many as 16 Kb ANDTM cells in a block are programmed and erased simultaneously. The erase operation is carried out by FN channel-erase, and program operation is carried out by FN edge-program. The edge-program is at the drain edge and cell structure is formed by buried N+ bit line and source line. The electrons are injected into cell""s floating gate by channel-erase operation with an increase in Vt. In contrast, the electrons are extracted out of the floating gate by edge-program operation with a decrease in Vt. Similarly, in the ANDTM flash cell, the drain junction of N+ is used for program operation only and is made to be much deeper than the source node surrounded with lightly-doped N-implant to reduce the peak electrical field as generated during drain-edge-program operation. The source junction is formed with shallow N+, with P+ implanted underneath to prevent voltage punch-through in short channel region during edge-program operation. Again, the ANDTM cell is made non-symmetrical with respect to source and drain junctions in terms of cell structure and operating conditions. Therefore, it is very difficult to shrink the ANDTM cell below 0.18 xcexcm technology for ultra-high integrated memory just as with the ETOXTM flash cell.
The key operating conditions for the one transistor ANDTM technology with the cell made on P-substrate are summarized below.
The drawbacks of the ANDTM flash cell are: a) low cell scalability due to asymmetrical cell structure with deeper drain junction; b) high program current due to edge-FN program scheme with huge substrate leakage current; and c) severe channel punch-through problem in shorter channel length cause by edge program operation.
The following U.S. patents of prior art are directed toward the detailed description of ANDTM flash cell operations:
A) U.S. Pat. No. 6,072,722 (Hirano) is directed toward programming and erasing a non-volatile semiconductor storage device.
B) U.S. Pat. No. 6,101,123 (Kato et al.) is directed toward programming and erasing verification of a non-volatile semiconductor memory.
C) U.S. Pat. No. 6,009,016 (Ishii et al.) is directed toward a nonvolatile semiconductor memory which recovers variation in the threshold of a memory cell due to disturbance related to a word line.
D) U.S. Pat. No. 5,982,668 (Ishii et al.) is directed toward a nonvolatile semiconductor memory which recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation.
E) U.S. Pat. No. 5,959,882 (Yoshida et al.) is directed toward a nonvolatile semiconductor memory device with a plurality o f threshold voltages set so as to store multi-valued information in one memory cell entitled.
F) U.S. Pat. No. 5,892,713 (Jyouno et al.) is directed toward a configuration that provides a nonvolatile semiconductor memory device which allows high-speed block reading.
G) U.S. Pat. No. 5,757,699 (Takeshima et al.) is directed toward the programming of a selected memory cell which is repeated until the programmed threshold voltage is not greater than a predetermined threshold voltage.
3) FN channel-erase, FN edge-program, One-transistor, NOR-type Flash EEPROM Technology. Like ANDTM flash technology, in this prior art, the program operation is performed on a bit-by-bit basis to decrease cell""s Vt while erase is performed on a block basis to increase cell""s Vt. Therefore, over-erase is not an issue. Both erase and program operations use the FN-tunneling method, which consumes only about 10 nA per bit without taking the greater substrate current into account. Therefore a large number of flash cells within a big block can be programmed and erased at one time by on-chip charge pump of economic area. For single low power supply Vdd of 3V or below, a larger number of flash cells in a block can be programmed and erased simultaneously as disclosed. In this prior art, the erase operation is carried out by FN channel-erase; program operation is carried out by FN edge-program. The edge-program is at the drain edge but the cell structure is formed by a non-buried N+ bit line and source line. The bit line is a vertical metal line, which connects all drains of the cells in the same block for high read speed. The source lines are tied together by N+ active line, which runs in parallel to the word lines. Each source line is shared by one pair of word lines as in ETOXTM flash cell array. As disclosed in this prior art, the electrons are removed from the floating gate of the cells by drain-edge-FN programming with a decrease in Vt. Conversely, the electrons are injected into the floating gate by channel-erase with an increase in Vt. Similarly, in this flash cell, the drain junction of N+ is used for FN-program operation and is made to be much deeper than source node, surrounding with lightly-doped N-implant to reduce the peak electrical field as generated during drain-edge-program operation. The source junction is formed with shallow N+ with P+ implant underneath to prevent voltage punch-through in short channel region during edge-program operation. Again, this flash cell is made asymmetrical with respect to source and drain junctions in terms of cell structure and operating conditions. Therefore it is again very difficult to be further shrunken for ultra-high integrated memory below 0.18 xcexcm technology.
The key operating conditions for this technology with cell made on P-substrate are summarized below.
The drawbacks of this type of flash cell are: a) low cell scalability due to asymmetrical cell structure with a deep drain junction; b) high program current due to edge-FN program scheme with a huge substrate leakage current; and c) severe channel punch-through problem in shorter channel lengths due to edge program. The details of this flash cell are disclosed in U.S. Pat. No. 5,708,600 (Hakozaki et al.) which is directed toward a method for writing a multiple value into a nonvolatile memory capable of multiple value data being written into a floating gate type memory cell.
4) FN channel-erase, FN edge-program, one transistor, NOR-type Flash EEPROM technology. This type of flash technology has the same advantage of over-erase-free as the ANDTM type flash cell, and provides higher flexibility in erase and program unit size. U.S. Pat. No. 5,748,538 (Lee et al) is commonly assigned to the owner of the present invention and refers to an OR-plane memory cell array. A plurality of transistor cells are arranged in rows and columns to form a flash electrically erasable programmable read only memory (EEPROM). In U.S. Pat. No. 5,848,000 (Lee et al.), commonly assigned to the owner of the present invention, a flash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. The invention includes high accuracy and flexibility to read, erase and program the flash memory.
The key operating conditions for this OR technology with the cell made on P-substrate are summarized below.
An object of the present invention is to provide a highly scalable flash EEPROM array configuration with the new erase and program schemes.
Another objective of the present invention is to use channel-erase and channel-program operations to remove the high voltage drop across the cell""s channel during FN edge-program operation and to permit use of a shorter channel length for ultra high density flash EEPROM memory.
Another further objective of the present invention is to use over-erase-free channel-erase and channel-program operations in the present invention for reliable read, program and erase operations.
Still another objective of the present invention is to provide a new type of channel-erase and channel-program method to write flash EEPROM of either block-size or page-size with immunity from over-erase.
Yet another objective of the present invention is to provide optimal voltages for word lines, bit lines, source lines and P-wells for Vt-increase erase and erase-verify operations so that the selected over-erased cells can be bit-by-bit effectively programmed with a very precise Vt distribution for storing multiple bits per cell.
Yet another further objective of the present invention is to provide optimal voltages for word lines, bit lines, source lines and P-wells for erase, correction, program and inhibit operations so that the disturbance of the Vt of non-selected cells can be eliminated or reduced.
Still yet another objective of the present invention is to provide optimal voltages for word lines, bit lines, source lines and P-wells to provide for a highly-scalable symmetrical cell.
Still yet another further objective of the present invention is to provide the optimal voltages for word lines, bit lines, source lines and P-wells so that the aforesaid drawbacks of severe channel punch-through and program current can be reduced for better life cycle and lower power consumption.